Field of the Invention
The invention relates to a circuit configuration for programming a delay in a signal path.
In integrated circuits, in particular in semiconductor memories of the dynamic type, what are referred to as DRAMs (Dynamic Random Access Memories), it is necessary for the same circuit design to be configured for different application purposes. In addition, there is a need to set functional properties in dependence on fluctuations in the manufacturing process. To do this, programmable connections, referred to a fuses, are conventionally used. These fuses can either be programmed to be switched on via an additional metal conductor track or programmed to be switched off by means of energy pulses. As a result, it is possible to set delays in signal paths within the DRAM, or a circuit design can be adapted to different module variants. The metal-programmable or fusible connections are referred to as metal options or fusible options.
Published German Patent Application DE 199 22 712 A1 discloses a phase interpolator with a delay interpolation circuit. Various signal paths whose delay can be varied are disclosed. The delay is achieved by means of respectively assigned currents with different current strengths. The currents are made available by thermometer digital/analog converters.
Published German Patent Application DE 41 12 077 A1 discloses a programmable logic module in which a delay stage is connected between a combinatorial logic operation circuit and the macro cell. The delay of the delay stage can be switched between two levels as a function of a control signal.
It is accordingly an object of the invention to provide a circuit for programming a delay in a signal path which overcomes the above-mentioned disadvantageous of the prior art apparatus of this general type. In particular, it is an object of the invention to provide such a circuit, which includes a particularly small number of components and which can be easily programmed.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for programming a delay in a signal path, which includes: an input terminal for receiving an input signal; an output terminal for providing an output signal; a first signal path section with a first delay, the first signal path section having an input end connected to the input terminal and having an output end; a second signal path section with a second delay that is different from the first delay of the first signal path section, the second signal path section having an input end connected to the input terminal and having an output end; and a multiplexer having an input connected to the output end of the first signal path section and the output end of the second signal path section, the multiplexer having an output connected to the output terminal. The circuit configuration also has a drive circuit that includes supply terminals for receiving a supply voltage, and a first path connected between the terminals for receiving the supply voltage. The first path includes two transistors connected together to define a first node. The first path includes a first programmable path section and a second programmable path section. One of the first programmable path section and the second programmable path section is programmed to be switched on and the other one of the first programmable path section and the second programmable path section is programmed to be switched off. The drive circuit also includes a second path that is connected between the terminals for receiving the supply voltage. The second path includes two transistors connected together to define a second node. The second path includes a first programmable path section and a second programmable path section. One of the first programmable path section of the second path and the second programmable path section of the second path is programmed to be switched on and another one of the first programmable path section of the second path and the second programmable path section of the second path is programmed to be switched off. The two transistors of the first path are controllable by complimentary control signals. The two transistors of the second path are also controllable by the complimentary control signals. The multiplexer has a control input that is connected to the first node and the second node.
The circuit configuration according to the invention has a small number of components. The two signal path sections have a different signal transit time are thus driven in parallel at the input end and each generate an output signal in accordance with their set delay. At the output end, just one of the two delayed signals made available is tapped. The multiplexer is used for this, and it selects one signal path section or the other by means of metal options or fusible options. The selection circuit is space-saving. The selection circuit includes four metal options or fusible options and four transistors having paths connected in the center. By means of a preset control signal, a setting of the drive circuit is selected and accordingly a setting of the multiplexer is selected. The significant factor is that just one of the options per path section is programmed to be switched on and the other is switched off.
In accordance with an added feature of the invention, the drive signal, which operates the drive circuit, is set by means of what is referred to as a bonding option. To do this, the drive signal is tapped by a terminal face, referred to as a bond pad, which is connected by a bonded connection to a terminal for the positive pole of the supply voltage or alternatively to a terminal for the negative pole of the supply voltage. In this way, the signal which presets the drive circuit has a predefined high level or low level.
To carry out the configuration, the drive circuit is first programmed with a metal option by means of the last mask while the semiconductor chip is being manufactured. Instead of the metal option, the fusible option can be used in which a connection is melted with a laser. After the integrated circuit has been tested, the precise desired delay is finally set by means of the bonding option. Overall, a flexible setting of a delay for a signal path is set with the possibility of intervening at various points in the manufacturing process of the integrated circuit.
In accordance with an additional feature of the invention, there is provided, capacitors and third programmable path sections for connecting the capacitors in either the first signal path section or the second signal path section.
In accordance with another feature of the invention, the two transistors of the first path include an n-type channel MOS transistor and p-type channel MOS transistor, and the two transistors of the second path include an n-type channel MOS transistor and p-type channel MOS transistor.
In accordance with a concomitant feature of the invention, the circuit configuration includes: a first metal line and a second metal line. The first programmable path section of the first path includes a first terminal connected to the first metal line when the first programmable path section is programmed to be switched on. The first terminal is not connected to the first metal line when the first programmable path section is programmed to be switched off. The second programmable path section of the second path includes a second terminal connected to the second metal line when the second programmable path section is programmed to be switched on. The second terminal is not connected to the second metal line when the second programmable path section is programmed to be switched off.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for programming a delay in a signal path, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description. of specific embodiments when read in connection with the accompanying drawings.